In a flat design flow, placement and routing resources are always visible and available. Designers then can perform routing optimization and avoid congestion to achieve a good-quality design ...

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.

Even when your design is targeting today's fastest FPGAs, achieving aggressive performance requirements can be a seemingly impossible task, especially with shrinking design schedules and other ...

To keep up with time-to-market demands when SoCs keep increasing in size and complexity requires the adoption of better DFT flows and technologies. One of the most successful changes in ...

Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to ...

SAN JOSE, Calif., Jan. 17, 2011 (GLOBE NEWSWIRE) -- Magma® Design Automation (Nasdaq:LAVA), today announced the availability of a proven hierarchical RTL-to-GDSII reference flow for the Common ...

Hierarchical design methodologies that introduce concurrency into the design flow are the answer to burgeoning circuit complexity. Synopsys's Steve Kister discusses various challenges to design ...