EDN

Renesas memory cell mixes SRAM, DRAM tech

Tokyo – Renesas Technology Corp. has developed a new SRAM memory cell structure that combines SRAM and DRAM technologies. The device is about half the size of a conventional SRAM cell, but still has ...
Semiconductor Engineering

Overcoming Challenges In Next-Generation SRAM Cell Architectures

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each ...
Design-Reuse

Low Power 7T SRAM Cell Scheme - ''Saving Write Zero Power''

This paper presents a Seven-transistor SRAM cell intended for the advanced microprocessor. A low power write scheme, which reduces SRAM power by using seven-transistor sense-amplifying memory cell, ...
Semiconductor Engineering

A Triple-Deck CFET Structure With An Integrated SRAM Cell For The 2nm Technology Node And Beyond

A novel triple-deck CFET structure is proposed for the first time as a candidate for area scaling. The proposed triple-deck CFET aggressively stacks a pass gate over an inverter to form a half SRAM ...
EDN

Renesas proofs SRAM memory cell against soft errors

TOKYO — Renesas Technology Corp. has developed an SRAM memory cell that it claims can reduce soft error rates at the same time as reducing cell size and power ...