Semiconductor Engineering

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

“Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency ...
Ars Technica

Rambus launches XDR2 DRAM with microthreading

Today Rambus launched XDR2, which is the successor to the existing XDR a.k.a. “Yellowstone” DRAM interface technology that’s being used in the PS3. XDR2 DRAM is essentially an evolutionary step over ...
EDN

DRAM tuning looks to speed graphics work

Fremont, Calif. – Graphics could be processed faster by breaking up the DRAM array into a bunch of smaller independent arrays with separate row and column decoders, Rambus engineers suggest. In a ...
Electronic Design

Overcome Traditional Memory-Speed Barriers With Embedded DRAM

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, ...
TweakTown

Samsung's new 1c DRAM yields improve: new chairman admits prior mistakes, but ready for HBM4

TL;DR: Samsung is set to launch next-gen HBM4 memory with its advanced 1c DRAM core die, targeting mass production in late 2025. Under Vice Chairman Jeon Young-hyun's leadership, Samsung aims to ...
EDN

400-MHz DDR DRAM face uncertain support

SANTA CLARA, Calif. — The latest flavor of double-data-rate DRAM is facing an uncertain future as memory vendors butt heads over whether the 400-MHz chips will go beyond “boutique” status and find ...